资源列表
axi_jesd204b
- ADI JESD204接口的ADC与Xilinx FPGA接口IP，包含Verilog和VHDL源代码，AXI总线接口，ADC串行控制接口-ADI IP for interfacing JESD204 ADC to Xilinx FPGA, include Verilog/VHDL source code, AXI interface and serial config interface
ad7298_nios
- AD7298 ADC的SOPC系统，包含AD7298 Avalon总线接口IP，SOPC系统，NIOS软件-AD7298 in SOPC system, include AD7298 avalon interface IP, sample SOPC system, NIOS software
ad7688_nios
- AD7688 ADC的SOPC系统，包含AD7688 Avalon总线接口IP，SOPC系统，NIOS软件-AD7688 ADC in SOPC system, include AD7688 avalon interface IP, sample SOPC system, NIOS software
c3_am_tx
- 使用CycloneIII FPGA实现纯数字AM发射机，播放WAVE格式的文件，通过FPGA数字调幅，从IO发射出去 -Use CycloneIII FPGA to achieve a digital AM transmitter, play WAVE format file, Digital AM modulation, transmitted by FPGA IO
c3_fm_tx
- 使用CycloneIII FPGA实现纯数字FM发射机，播放WAVE格式的文件，通过FPGA数字调频，从IO发射出去-Use CycloneIII FPGA to achieve a digital FM transmitter, play WAVE format file, Digital FM modulation, transmitted by FPGA IO
AWGN_VerilogDesign-master
- 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
mealy_0011_detector
- Key detector a given bit stream-Key detector a given bit stream
shuzijishiqi
- 基于VHDL的数字计时器，手动可控正计时和倒计时(含复位键和使能键)-VHDL-based digital timer and countdown timer being controlled manually (with the reset button and enable key)
memoria
- this file contain a simple example of a memory eeprom using vhdl
counter60
- 基于FPGA的模60计数器，实现0-59计数，四个数码管后两个显示十位和个位，拨盘按钮P11为复位键。-FPGA-based mold 60 counters to achieve 0-59 counts, two of the four digital tube display after ten and a bit, dial button P11 for the reset button.
60
- 利用实验板实现模六十计数，即00—01—02—03—04—…59—00—01…，并在Basys2实验板的AN1~AN0与（LD7~LD0）上显示-Experimental plate to achieve mode 60 counts, namely 00-01-02-03-04- ... 59-00-01 ... AN1 ~ AN0 Basys2 experiment board with
source_code
- 应用于可见光中的OOK调制，传1的时候传送一个周期正弦波，发0的时候传送1- Applied to the visible light in the OOK modulation, the transmission of a period of 1 times a sine wave, 0 of the time to send 1