资源列表
skeleton
- two component VHDL code in skeleton
UART
- UART (serial) protocol in VHDL with receive & send
intra4x4
- Intra4x4 in VHDL for H.264 encoder. this module work with 3 intra prediction mode
edge_detector_logic
- verilog code for edge detection logic
seg_example
- DE2-115 seg example source code
des
- 具有所有的DES等加密解密运算操作实现，加密，解密等运算-verilog DES encrypt
class_fifo
- FPGA内部fifo的调用,使用Verilog对其进行编程-The FPGA internal fifo calls, use Verilog programming on it
class11_uart_tx
- 主要是使用Verilog代码编程的串口发送程序-Mainly use Verilog code programming serial port to send the program
class11_uart_rx
- 主要使用Verilog代码编程的串口接收程序-Mainly use Verilog code programming serial port to receive
class19_IR_code
- 主要是运用Verilog代码对红外进行解码-Mainly use Verilog code to decode the infrared
class10_HEX8
- 主要是用Verilog代码编程对8位数码管的显示的控制-Mainly use Verilog code programming control of eight digital tube display
mul_addtree
- 8位加法树乘法器Addition tree multiplier-Addition tree multiplier of 8bits