资源列表
dds_using_FPGA
- 利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2，该环境集成了IP核，可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
watchver
- 一个VHDL编写的时钟的程序，全部源代码打包上传-The clock to prepare a VHDL process, all source code packaged Upload
CY62256VSO
- 用VHDL编写的CY62256VSO芯片的驱动程序.-CY62256VSO prepared using VHDL chip driver.
ICdesignVHDLbookofthesourcefile
- 《集成电路设计VHDL教程》一书中的源文件-" IC design VHDL Tutorial," a book of the source file
adc
- vhdl实现对模数转换芯片adc0832的控制,程序采用的是状态编码输出.-VHDL realization of analog-digital conversion chip adc0832 control, procedures using state of the output encoding.
uart
- 用vhdl实现的串口通信程序,可以综合并下载到FPGA运行.-Achieved using VHDL serial communication procedures, can be synthesized and downloaded to the FPGA to run.
KX_DVP3F_SCH
- 康芯FPGA开发竞赛板kx-dvp3f的电路图-Kangxin FPGA development board kx-dvp3f circuit race
bingchuan
- 自己编写的并串变换的fpga程序，使用verilog语言-I have written and strings Transform FPGA procedures, the use of Verilog language
chuanbing
- 自己编写的串并变换的fpga程序，使用verilog语言-I have written FPGA series and transform, the use of Verilog language
61EDA_D702
- 4位电子智能密码锁，基于VHDL语言设计，MAX+PLUSⅡ环境下实现-4 electronic smart locks, based on the VHDL design language, MAX+ PLUS Ⅱ environment to achieve
VHDL
- 一本关于VHDL的书，内容很详细，是初学入门的好书-VHDL on a book, the contents in detail is the beginning of the book entry
dp_test
- 本程序是用VHDL语言编写的，其中包括并口通讯，DDS电机调速,编码器信号处理等，对研究这方面的工程人员有一定参考作用-This procedure is used VHDL language, including the parallel port communication, DDS motor, encoder signal processing and so on, to look at this area of engineering staff have a certain refe