资源列表
Quartus2_VerilogRoutine
- 该文档是基于QUARTUS2_6.0的Verilog试验例程，其中附有工程源码，对于初学者是最好的例程！它是本人花费一年多自学后写的例程，以便初学者入门，里面附有很多图解，很详细！-The document is based on the Verilog test QUARTUS2_6.0 routines, including an engineering source code, for beginners is the best routine! It is, I spent more
bb
- CPLD可编程逻辑芯片上实现信号发生器的方法和步骤，系统采用自顶向下的设计方法，以硬件描述语言VHDL和原理图为设计输入，利用模块化单元构建系统。-CPLD programmable logic chip Signal Generator methods and steps system uses top-down design approach to hardware descr iption language VHDL and principles of map design input,
VHDL-Cookbook
- VHDL快速查看 入门手册 还有少量精品例子-VHDL Quick View Getting Started manual was also a small number of fine examples
vhdlexample
- vhdl简单的例子程序，供初学者参考，有模板可以参考-VHDL example of a simple procedure, the reference for beginners, it can refer to the template
datapath
- for FPGA IMPLEMENTATION,OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION-for FPGA IMPLEMENTATION, OUR DATAPATH CREATED FOR TWO BIRS MULTIPLICATION
matrix
- Implement the Matrix function about 16bits on FPGA BOARD
hdladvance
- Advanced HDL Design Training On Xilinx FPGA-Advanced HDL DesignTraining On Xilinx FPGA
verilog_slides
- What is Verilog? ➥ Verilog HDL is a Hardware Descr iption Language (HDL) ➥ Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels ➥ Primary use of HDLs is the simulation
verilog_intr
- Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks –
vhdl_intr
- 1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the design environments – Simulation – Synthesis-1. Learn the basic constructs of VHDL2. Learn the modeling structure of VHDL3. Understand the design
VHDL_note
- VHDL是由美国国防部为描述电子电路所开发的一种语言，其全称为(Very High Speed Integrated Circuit) Hardware Descr iption Language。 与另外一门硬件描述语言Verilog HDL相比，VHDL更善于描述高层的一些设计，包括系统级（算法、数据通路、控制）和行为级（寄存器传输级），而且VHDL具有设计重用、大型设计能力、可读性强、易于编译等优点逐渐受到硬件设计者的青睐。但是，VHDL是一门语法相当严格的语言，易学性差，特别是对于刚开始
clock_module_ref
- Xilinx clock module design