资源列表
VHDL100
- VHDL语言100例，通过例子了解VHDL语言。-VHDL language of 100 cases, through the example of VHDL language understanding.
vga_card
- VGA模块的VHDL代码和软件驱动，可作为外设挂接在Avalon总线上。用一块SRAM作为显存，双缓存切换模式。-VGA module VHDL code and software drivers can be articulated as a peripheral bus in Avalon. As with a piece of SRAM memory, dual-mode cache switching.
shuzizhongdianlu
- 利用计数器和分频器设计一个实时的时钟。一共需要1个模24计数器、2个模6计数器、2个模10计数器、一个生成1Hz的分频器和6个数码管解码器。最终用HEX5~HEX4显示小时（0~23），用HEX3~HEX2显示分钟（0~59），用HEX1~HEX0显示秒钟（0~59）。 -The use of counters and prescaler design a real-time clock. Mold needs a total of 24 counters, 2 Die 6 counters,
VHDLexamples
- VHDL案例代码，配套雷伏荣编的《VHDL电路设计》-Case VHDL code, matching Lei Fu-rong series "VHDL Circuit Design"
cam_test
- 一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog-CAM a verified source (CAM = Content Address Memory). Language for Verilog
AVR_Core.tar
- vhdl语言编写的AVR单片机IP核，里面有testbench和说明文档。-VHDL language AVR Single Chip IP core, there are Testbench and documentation.
Xilinx
- Xilinx可编程逻辑器件的高级应用与设计技巧 全面介绍Xilinx的CoolRunnerII Spartan-3 Virtex-II VirtexII pro等器件的结构特性，以及ISE6及其辅助设计工具。 -Xilinx programmable logic devices and design techniques for advanced applications a comprehensive introduction to Xilinx s CoolRunnerII Sparta
PKUverilogPPT1-9PAGE
- 课件 北京大学verilogHDL PPT课件-Peking University verilogHDL PPT Courseware Courseware
SYNTHPIC.ZIP
- The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the licen
FIFO_2
- VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
ADC_16bit
- VERILOG 16-bit Analogue-Digital Converter-VERILOG16-bit Analogue-Digital Converter
zhongbiao
- VHDL的数字电子钟程序，供初学者参考哦！-VHDL digital electronic clock procedures, for beginners reference Oh!