搜索资源列表
vhdldds0000
- 采用fpga的hdl语言实现dds的信号发生器的设计，性能与传统相比明显提高。-Hdl language using FPGA implementation of the signal generator dds design, performance markedly improved compared with the traditional.
xapp851
- The xapp851.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \rtl - HDL design files \sim - simulation files \synth - Synthesis related files \par - Place/Route related files-The xapp
test1
- 4位数字频率计的verilog HDL设计，精度比较准的-4-digit Cymometer verilog HDL design, the accuracy of the quasi-comparison
yuvrgb
- 将yuv4：2：2的图像数据转为rgb格式，用Verilog HDL编写-yuv4：2：2 to rgb
vgatest
- 用verilog HDL写的VGA驱动，在FPGA上实测可用（实际上是别人的劳动成果，呵呵）。-VGA driver coded in Verilog HDL. Tested.
hdl
- 网上流传的用来实现FPGA驱动VGA，从而实现一个pingpong小游戏的源码，实测可用。-a program embedded in a FPGA in order to drive the VGA and realize a little game named pingpong. tested.
Verilog_quick_reference
- Verilog HDL 的快速入门，是网页格式。非常实用，包括语法、运算符等方面。-a useful quick reference of Verilog HDL. Especially for the starters like me!
chinese_version_of_the_gold_reference_for_Verilog.
- Verilog_黄金参考中文版,共HDL开发的朋友使用，要珍惜哦！-Gold reference Verilog_ Chinexe version of Friends of the total development of the use of HDL, it is necessary to cherish Oh!
lcd
- lcd1602的源程序Vrilog HDL语言编写-Vrilog HDL source lcd1602 languages
adder8
- Vrilog HDL 八位加法器源程序-8 adder Vrilog HDL source
my_and
- 此实验例程适用于Actel Flash架构的ProASIC3/E系列FPGA，适合于FPGA及Verilog HDL的初学者，配套EasyFPGA030开发套件。-Routine application of this experiment in the Actel Flash architecture ProASIC3/E series FPGA, fit in the FPGA and Verilog HDL for beginners and supporting development
memory_example
- This simple example allows you to get familiar with Active-HDL s Memory Viewer.
veriloghdlcsdm
- 用verilog hdl 硬件描述语言写的一个范例程序，led的，扩展性极强，欢迎大家下载使用。-Verilog hdl using hardware descr iption language to write an example of the procedure, led, and highly scalable, welcome to download.
multicycle
- 多周期处理器--verilog写的,欢迎大家来下载，-multicycle microprocessor written with verilog HDL
VerilogHDL
- VERILOG HDL 华为公司的入门教程 内部资料，很有启发-VERILOG HDL Tutorial Huawei s internal information, very enlightening
DA_TLC5620
- 用verilong hdl语言编写的数据采样程序，A/D采用的是TLC5260-Verilong hdl language used data sampling procedures, A/D using the TLC5260
DW8051_verilog
- DW8051单片机的设计，用HDL设计，详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL
hdl
- 用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures
fifo8
- FIFO 源程序，verilog HDL实现，自己验证过，没问题-FIFO source, verilog HDL to achieve their own verified, no problem
ide
- ide 的HDL描述.有接口和时续-HDL descr iption of the ide. when there is interface and continued