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16bit_multiply
- 一个16位并行乘法器, 已经进过功能验证, 可以用于综合。 -a 16bit parallel multiply after verification, can be used to synthesis
multiplier
- 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是:乘法通过逐项移位相加原理来实现,从被乘数的最低位开始,若为1,则乘数左移后与上一次的和相加;若为0,左移后以全零相加,直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplica
VHDL
- VHDL对各种电路的基本实现,包括乘法器,触发器,加减法器等-VHDL for the basic realization of the various circuits, including multipliers, flip-flops, and other instruments used in addition and subtraction
Multiple
- 高效的乘法器设计,既节约面积,又提高性能,同时减少开发周期-Efficient multiplier design, both to save space and improve performance while reducing the development cycle
FPGA
- 基于FPGA数字乘法器的设计:数字乘法嚣是目前数字信号处理中运用最广泛的执行部件之一,本文设计了三种基于FPGA 的数字乘法器.分别是移位相加乘法嚣、加法器树乘法器和移位相加一加法嚣树混合乘法器。通过对三种方案的仿真综合以厦速度和面积的比较指出了混合乘法器是其中最佳的设计方案-FPGA-based digital multiplier design: the number of multiplicative noise is the use of digital signal processin
multiprocessor
- 简单的乘法器的内核测试,已经验证通过,VLOGER编写-The core of a simple multiplier tests have verified through, VLOGER prepared
mutiplier
- 用VHDL语言仿真乘法器设计, 经过modelsim仿真, synplify综合,并下载进FPGA验证-Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification
multi
- 8位乘法器,Quters编译环境VHDL代码-pluter VHDL Quters
Lab4
- 实现原码一位乘法器,但必须位数相同才行。-hdbadbkwdk
16bit_mult
- 16位的无符号数乘法器,自己写的,经得起验证,注释很详细-16-bit unsigned multiplier, its own written
maths
- multiplux,8*8的单片机乘法器-for the microcontroller
8bit_mult
- 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
doublemult
- 设计了一个双精度浮点乘法器。该器件采用改进的BOO TH 算法产生部分积, 用阵列和 树的混合结构实现对部分积的相加, 同时, 还采用了快速的四舍五入算法, 以提高乘法器的性能。把 设计的乘法器分为4 级流水线, 用FPGA 进行了仿真验证, 结果正确 并对FPGA 实现的时序结果 进行了分析。-Designed a double-precision floating-point multiplier. The device uses an improved algorithm fo
matrix3x3
- 3*3矩阵的乘法器代码!!! !!! !!! !!!!1-3* 3 matrix multiplier code~
multiplier8x8
- 8位定点乘法器,支持有符号数/无符号数运算。采用4-2压缩树结构,并提供testbench。-It is an 8-bit fixed-point multiplier, supporting signed/unsigned operations. Wallance tree structure with 4-2 compression. Provides testbench.
mul8b
- 有VerilogHDL编写的8位乘法器,可以综合。-Have been prepared in 8-bit multiplier VerilogHDL can be integrated.
4_bit_mul
- 四位乘法器,可以实现两个四位二进制数的乘法。-4_bit_mul
BBooth
- 基verilog 布斯乘法器 4位位宽,本人不才,仅做参考-Booth multiplier based verilog
jiaotongdengsheji
- 乘法器 简单的乘法器编译 用VHDL自己编的-Compiled using a simple multiplier multiplier VHDL own series
6345252
- FPGA应用实例,FPGA片上硬件乘法器的使用,编程语言vhdl-Application FPGA, FPGA-chip hardware multiplier to use, programming language vhdl