资源列表
D_flop
- D触发器，用于搭建各种时序逻辑电路，是最常用的触发器。目前超大规模集成电路中皆使用该触发器。-D flip-flops used to set up the various timing logic circuit, is the most common trigger. VLSI are using the trigger.
fifo_syn
- 实现了同步FIFO的功能，能完成数据的先进先出，当FIFO满或者空的时候能报出满或者空的信号。-Synchronous FIFO: it can complete data FIFO, when the FIFO full or empty time can you quote us full or empty signal.
odd_division
- 实现了时钟奇数（11）分频器，其它奇数分频只要重新计算div1和div2参数就行了。-Realize the clock odd (11) frequency divider, other odd frequency division as long as recount div1 and div2 parameters will do.
detector_Moore
- 该程序实现了序列101101的检测，每当检测到该序列就输出1，采用了Moore型状态机。-This procedure realize the series 101101 detection, whenever detection to the sequence is output 1, the Moore type state machine.
sale_newspaper
- 该程序实现了自动售报纸的机器，能够自动找零，输入的硬币有1、2、5分三种，报纸每份5分。-The program has realized automatic sell newspaper machine, automatically change, input COINS have 1, 2, 5 points three, newspapers every 5 minutes.
Altera-FPGA-DE0
- Altera FPGA DE0的原理图 包含一些经典的FPGA设计电路及相关的接口-The Altera FPGA DE0 schematic contains the a classic FPGA design circuits and interface
BlockRam
- xilinx FPGA BlockRam source.
BramCfg
- xilinx FPGA BramCfg source.
BramComCtrl
- xilinx FPGA BramComCtrl source.
EppCtrlAsync
- xilinx FPGA EppCtrlAsync source.
KIEMTRA3_1
- Mo phong LEd sang chay vong vong
Shift
- the this file a module shift a bit of 32 bits. it contains shift left and shift right. thank for visiting