资源列表
88dianzhen
- 用VHDL语言编写的8*8点阵显示“北京08”的程序。可以用FPGA实现。可将程序当中的“北京08”改成别的汉字显示。-VHDL language using 8* 8 dot matrix display, " Beijing 08" procedures. FPGA implementation can be used. Procedures which could be the " Beijing 08" be changed to show the o
ACTEL-FPGA-1602(Verilog)
- 1602液晶显示程序，用verilog写的！-1602 LCD program, written using verilog!
ps
- VHDL语言编写的串并转换模块的源代码,用来将并行输入数据转换为串行数据输出-code for the transform of ps
ths5651
- ths5651的驱动程序，应用于cyclone 1c12，电子设计大赛使用过的-ths5651 driver, used in the cyclone 1c12 used by the Electronic Design Contest
Verilog
- 田耘《无线通信FPGA设计》书中例子的Verilog代码-Tian Yun, " Wireless Communications FPGA design" book example of Verilog code
DCM
- ISE实现DCM组建例化，得到3倍频时钟-ISE to achieve established cases of DCM, received 3 octave clock
DE1_i2sound
- Good vhdl code for WM8731
1chipmsx-cd
- VHDL实现的任天堂NES游戏系统，包含了CPU，APG，GPU等各个器件，可以下载到FPGA开发板上运行-VHDL implementation of the Nintendo NES game system includes a CPU, APG, GPU and other various devices, can be downloaded to the FPGA development board to run
multiplyingunit
- 其乘法器原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位-Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the l
VGA
- 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram
EEPROMVerilog-HDL
- EEPROM的Verilog HDL源代码，代码全-EEPROM of the Verilog HDL source code, code all. . . . . . . .
LCD12864
- 利用FPGA在12864液晶屏上显示汉字。配置IO后可直接使用-Use of FPGA in the 12864 character LCD display. IO configuration can be used directly after