资源列表
mp3
- MP3音频解码的verilog源代码，已经验证过的，可综合-MP3 Audio coding
comp_16
- 设计16位同步计数器 要求：（1）分析16位同步计数器结构和电路特点； （2）用硬件描述语言进行设计； （3）编写测试仿真并进行仿真。-Design 16-bit synchronous counter requirements: (1) analysis of the 16-bit synchronous counter and circuit characteristics (2) hardware descr iption language design (3) pre
PS2MAUSE
- 用VERILOG语言写的PS2鼠标驱动程序,用来读取鼠标的状态信息-PS2 MOUSE DRIVER
mcst
- 曼彻斯特编码实现，verilog HDL 做的，我也是从网上下的-Manchester encoding to achieve, verilog HDL to do, I am also from the Internet under
CPU
- 八位简单risc cpu 设计的源代码，VHDL语言写的-8 Simple risc cpu design source code, VHDL language written
FPGA-DE1-PACMAN
- Pacman 4 DE1-FPGA-Board
alu
- 用Verilog编写的简单的运算单元（ALU），可实现加、减、与、或、异或、非、左、右移等功能-Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right
NiosII_clock
- 用NiosII实现的数字钟，经过本人测试运行正常，开发环境：QuartusII6.0和NiosII IDE6.0-NiosII achieved with digital clock, after I run the normal tests, development environment: QuartusII6.0 and NiosII IDE6.0
8-bit
- 最基本的vhdl運算，採用8bit作乘法器，將兩串8bit的值輸入之後進行相乘-VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
open_cores_VGAcore
- 老外写的基于wishbone总线协议的VGA核控制器,Verilog版本适合于初学者学习VGA核控制器的原理以及总线协议的把握-Written by foreigners wishbone bus protocol based on the nuclear VGA controller, Verilog version is suitable for beginners to learn the principles of the controller and the VGA core gras
mydesign
- FPGA实现简易数字频率计设计。自己设计，绝对原创-FPGA realization of simple digital frequency meter design. Their own design, an absolute original
wannianli
- 采用VHDL语言编写的万年历程序，可在液晶上显示！-Using VHDL language calendar procedures, can be displayed on the LCD!