资源列表
crc12_4
- 数据位宽为4，crc12，verilog编写-crc12 datawidth is 4，coding by verilog
crc16_8
- crc16,数据位宽为8，verilog编码-crc16 ,datawidth is 8,coding by verilog
crc32_8
- crc32,数据位宽为8，verilog编码-crc32，datawidth is8,coding by verilog
crc_ccit_8
- crc_ccit, 数据位宽为8，verilog编码-crc_ccit, datawidth is 8,coding by verilog
AD
- 基于ADC0809的数据采集系统，对0~5V电压采集，显示到数码管显示-ADC0809 based data acquisition system, for 0 ~ 5V voltage of the collection, display to the digital tube display
x3cs400_uart
- 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
xge_mac
- 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below.
method
- i need to refer and search for calculator verilog.hope i can find answer from it.
61EDA_K4
- vhdl的引脚分布， vhdl的引脚分布，-vhdl
seuVerilog
- 基于导频的ofem系统的信道估计和均衡Verilog建模-ceu Verilog
61EDA_H182
- ram模块的Verilog程序的实现，还有好多的字要打-ram modules, Verilog program implementation, there are a lot of words Yaoda