- r4FFT_IFFTuseFPGA 64点基
- SingleLineTransformationMethodTest Activity Instrumentation Test Case2 Source Code for Andriod.
- Turbo-PMAC-Training(April2011) PMAC的一个很全的较好的培训资料
- nafise neural network to number recognition
- stl_stack Returns a read write reference to the data at the first element of the stack.
- pv--liao 光伏电池simulink仿真模型 光伏电池simulink仿真模型 光伏电池simulink仿真模型 光伏电池simulink仿真模型 光伏电池simulink仿真模型
资源列表
OV7670
- 摄像头模块OV7670中文版，方便快速熟悉OV7670的手册(The Chinese version of the camera module OV7670)
uart_design
- UART设计的VERILOG代码，具有FIFO功能，能实现CPU与外设之间的数据与指令通信(The VERILOG code designed by UART, which has the function of FIFO, can realize the communication between the data and the instruction between the CPU and the peripherals)
OV7670_
- ov7670是数据手册 对于ov7670的驱动很有帮助-ov7670 ov7670 drive helpful Data Sheet
LCD1602
- 基于FPGA 的1602显示源代码，可以直接使用-FPGA based 1602 show source code can be used directly
Massive Shifter
- Massive Shifter in VHDL, required in Matrix-Vector operations
VHDL
- 自己收集的VHDL例程代码，适合初学者学习用，希望能给大家带来帮助。-Collected their own routines VHDL code, suitable for beginners to learn, I hope we can help.
VHDL_Code
- 描写nco的完整程序，采用很简介的算法，对大家应该很有用-The complete program descr iption nco, using a very brief introduction of the algorithm, we should be very useful
dac
- 用VhdL编程控制芯片实现D/A转换。-VhdL the realization of D/A conversion.
time_test
- 利用10M的时钟，设计一个单周期形状的周期波形。这是用Verilog写的-Use 10M clock cycle design a single cycle waveform shape. This is written in Verilog
heartbeat
- 用VHDL编译的源代码，模仿心脏跳动，解压后直接用Quartus打开project即可-Compiled with VHDL source code, mimic the heart beating, after extracting the direct use of Quartus can open the project
ALU2
- VHDL 做的ALU ，我们的实验代码,已经验证，可以使用-VHDL do ALU, our experimental code, has been verified, you can use
50602
- vhdl语言实现电子时钟设计 时分秒 可以设置-vhdl language designed to achieve accurate electronic clock can be set