资源列表
ram
- VHDL 编写的RAM例子
vga
- VHDL 语言如何写VGA的源代码，很详细的-VHDL for VGA
DDS_verilog
- 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
sin
- FPGA正弦波信号发生器，能产生完美的正弦波形-FPGA sine wave signal generator, can produce perfect sine wave
traffic
- 交通灯实验 用PLC实验台调试 成功 交通灯-traffic light
verilog-counter
- 利用Verilog实现的数字钟和汽车尾灯，有闹钟，报时，置数等多种功能-Verilog
ad_max11046
- 基于nios2系统的mx11046的初始化，采样，写命令，读数据，以及一些优化设置。-Based on mx11046 nios2 system initialization, sampling, write commands, read data, and some optimization Settings
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
cic_filter
- 5阶cic滤波器 使用vdhl编写 下载后将tb代码烤出 新建，然后综合仿真！-5 cic filter using vdhl written order to download the code will tb baked New, and then integrated simulation!
s_mips
- FPGA verilog mips processor - pipeline reference
piccolo
- piccolo 密码算法的Verilog实现-piccolo algorithm
bysj
- 基于FPGA 的数控移相正弦信号发生器。-FPGA-based CNC phase-shifted sinusoidal signal generator.