资源列表
experiment
- 4位十进制频率计设计，程序详细，可以直接应用-4 decimal frequency meter design, program details, can be applied directly
ExamplesofVHDLDescriptions
- 含有大量EDA实验，全文为英语书写，例子采用VHDL语言。-EDA with a large number of experiments, the full text is written in English, examples using VHDL language.
VHDL
- 包含有44例具体详细的VHDL实验说明及程序。-Contains a detailed 44 cases of specific experimental instructions and procedures VHDL.
XilinxOneWireInterface
- Xilinx公司的1 wire接口HDL源代码，可以用来读取1 wire的rom。-Xilinx Inc. 1 wire interface to HDL source code, can be used to read the 1 wire in the rom.
dual
- This module defines a Synchronous Dual Port Random Access Memory.
cpld_2440_c
- 用ispLEVER Starter软件开发的工程，逻辑用VHDL语言编写，源文件为ARMSYS2440CPLD.VHD 用于ARM2440控制CPLD-ARM2440_CPLD
add
- 一个加法器，用VHDL写的程序，七位加法器，在V5的芯片上试过了-one adder
seqdet
- 串行序列检测器，以得到modelsim仿真波形，用verilog编写。-Serial sequence detector to get modelsim simulation waveform, prepared with verilog.
CLK_5
- verilog实现时钟的奇数分频，通过ISE仿真。-verilog to achieve the odd clock frequency, by ISE simulation.
LD
- verilog语言实现LD灯的轮流点亮，下载到板子，验证了的。下载即可在ISE中实现仿真。-verilog language LD lights turn lights, downloaded to the board to verify the. Downloads can be realized in the ISE simulation.
LED
- 实现数码管的秒。分钟位显示。时钟1s调一次，下载到板子，通过验证了的verilog程序-To achieve digital control of the second. Minute digital display. 1s adjusted clock time, downloaded to the board, through the verilog program verified
vhdl_math_tricks
- VHDL语言中如何使用数据，加减乘除和类型转换，对FPGA进行数值计算的人非常有价值的文章-VHDL language how to use the data, Math, and type conversion, the very valuable article for FPGA numerical calculation